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| Back CS5421 Dual Out-of-Phase Synchronous Buck Controller with Remote Sense The CS5421 is a dual N-channel synchronous buck regulator controller. It contains all the circuitry required for two independent buck regulators and utilizes the V2TM control method to achieve the fastest possible transient response and best overall regulation, while using the least number of external components. The CS5421 features out-of-phase synchronization between the channels, reducing the input filter requirement. The CS5421 also provides undervoltage lockout, Soft Start, built in adaptive FET non-overlap and remote sense capability. The part is available in a 16 Lead SO Narrow package allowing the designer to minimize solution size. Features * V2 Control Topology * 150 ns Transient Response * Programmable Soft Start * 25 ns Gate Rise and Fall Times (with 1.0 nF load) * 40 ns Adaptive FET Nonoverlap Time * 100% Duty Cycle for Enhanced Transient Response * Internal Slope Compensation * 1.0 V 0.8% and 2.0% Error Amplifier References * 150 kHz to 750 kHz Programmable Frequency Operation * Switching Frequency Set by Single Resistor * Out-Of-Phase Synchronization Between the Channels Reduces the Input Filter Requirement * Undervoltage Lockout * On/Off Control Through Use of the COMP Pins http://onsemi.com SO-16 D SUFFIX CASE 751B PIN CONNECTIONS AND MARKING DIAGRAM 1 GATE(H)1 GATE(L)1 PGND LGND SGND VFFB1 VFB1 COMP1 16 GATE(H)2 GATE(L)2 PGND2 VCC ROSC VFFB2 VFB2 COMP2 CS5421 AWLYWW A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS5421GD16 CS5421GDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel (c) Semiconductor Components Industries, LLC, 2001 1 May, 2001 - Rev. 9 Publication Order Number: CS5421/D CS5421 VIN 5.0 V VIN 12 V 1.0 H 3 x 1200 F VOUT 3.3 V/11 A 1.2 H 15 4 x 1200 F 14 11 9 0.1 F 10 34.5 k 12 16 1.0 F 13 VCC GATE(H)2 GATE(H)1 1 2.7 H 3 x 1200 F VOUT 1.5 V/9.0 A 6 x 1200 F GATE(L)2 PGND2 VFFB2 COMP2 VFB2 ROSC GATE(L)2 2 3 6 8 0.1 F CS5421 PGND1 VFFB1 COMP1 VFB1 7 LGND 4 SGND 5 30 k 15 k GND SENSE 15 k 30.9 k Figure 1. Application Diagram, 5.0 V/12 V to 3.3 V/11 A and 1.5 V/9.0 A Converter for Processor I/O and Core Supplies ABSOLUTE MAXIMUM RATINGS* Rating Operating Junction Temperature, TJ Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Package Thermal Resistance: Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1.) Value 150 -65 to +150 2.0 28 115 230 peak Unit C C kV C/W C/W C ABSOLUTE MAXIMUM RATINGS Pin Symbol VCC COMP1, COMP2 VFB1, VFB2 VFB1, VFB2 Pin Name IC Power Input Compensation Capacitor for Channel 1 or 2 Voltage Feedback Input for Channel 1 or 2 Fast Voltage Feedback Input for Channel 1 or 2 VMAX 16 V 4.0 V 5.0 V 5.0 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V ISOURCE N/A 1.0 mA 1.0 mA 1.0 mA ISINK 1.5 A peak 200 mA DC 1.0 mA 1.0 mA 1.0 mA http://onsemi.com 2 CS5421 ABSOLUTE MAXIMUM RATINGS (continued) Pin Symbol ROSC GATE(H)1, GATE(H)2 GATE(L)1, GATE(L)2 PGND1 PGND2 SGND LGND Pin Name Oscillator Resistor High-Side FET Driver for Channel 1 or 2 Low-Side FET Driver for Channel 1 or 2 Power Ground for Channel 1 Power Ground for Channel 2 Ground for Internal Reference Logic Ground VMAX 4.0 V 16 V 16 V 0V 0V 150 mV 0V VMIN -0.3 V -0.3 V -0.3 V 0V 0V 0V 0V ISOURCE 1.0 mA 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC 1.0 mA 50 mA ISINK 1.0 mA 1.5 A peak 200 mA DC 1.5 A peak 200 mA DC N/A N/A N/A N/A ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 125C; ROSC = 30.9 k, CCOMP1,2 = 0.1 F, 10.8 V < VCC < 13.2 V; CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.) Characteristic Error Amplifier VFB1(2) Bias Current COMP1,2 Source Current COMP1,2 Sink Current Reference Voltage 1 Reference Voltage 2 COMP1,2 Max Voltage COMP1,2 Min Voltage Open Loop Gain Unity Gain Band Width PSRR @ 1.0 kHz Transconductance Output Impedance GATE(H) and GATE(L) High Voltage (AC) Low Voltage (AC) Rise Time Fall Time GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay GATE(H)1(2) and GATE(L)1(2) pull-down Measure: VCC - GATE(L)1,2; VCC - GATE(H)1,2; Note 2. Measure:GATE(L)1,2 or GATE(H)1,2; Note 2. 1.5 V < GATE(L)1,2 < VCC - 1.5 V 1.5 V < GATE(H)1,2 < VCC - 1.5 V VCC - 1.5 > GATE(L)1,2 > 1.5 V VCC - 1.5 > GATE(H)1,2 > 1.5 V GATE(H)1,2 < 1.0 V, GATE(L)1,2 > 1.0 V GATE(L)1,2 < 1.0 V, GATE(H)1,2 > 1.0 V Resistance to PGND Note 2. - - - - 40 40 50 0 0 25 20 70 70 125 0.5 0.5 60 60 100 100 280 V V ns ns ns ns k VFB1(2) = 0 V COMP1,2 = 1.2 V to 2.5 V; VFB1(2) = 0.8 V COMP1,2 = 1.2 V; VFB1(2) = 1.2 V COMP1 = VFB1; 25C < TJ < 125C COMP2 = VFB2 VFB1(2) = 0.8 V VFB1(2) = 1.2 V - - - - - - 15 15 0.992 0.980 3.0 - - - - - - 0.1 30 30 1.000 1.000 3.3 0.25 95 40 70 32 2.5 1.0 60 60 1.008 1.020 - 0.35 - - - - - A A A V V V V dB kHz dB mmho M Test Conditions Min Typ Max Unit 2. Guaranteed by design, not 100% tested in production. http://onsemi.com 3 CS5421 ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 125C; ROSC = 30.9 k, CCOMP1,2 = 0.1 F, 10.8 V < VCC < 13.2 V; CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.) Characteristic PWM Comparator Transient Response PWM Comparator Offset Artificial Ramp VFFB1(2) Bias Current VFFB1(2) Input Range Minimum Pulse Width Oscillator Switching Frequency Switching Frequency Switching Frequency ROSC Voltage Phase Difference Supply Currents VCC Current SGND Current Undervoltage Lockout Start Threshold Stop Threshold Hysteresis GATE(H) Switching; COMP1,2 charging GATE(H) not switching; COMP1,2 discharging Start-Stop 7.8 7.0 0.5 8.6 7.8 0.8 9.6 8.6 1.5 V V V COMP1,2 = 0 V (No Switching) - - 75 16 150 22 225 mA A ROSC = 61.9 k; Measure GATE(H)2, Note 3. ROSC = 30.9 k; Measure GATE(H)2 ROSC = 11.8 k; Measure GATE(H)2, Note 3. ROSC = 30.9 k, Note 3. - 112 224 600 0.970 - 150 300 750 1.000 180 188 376 900 1.030 - kHz kHz kHz V COMP1,2 = 1.0 V, VFB1(2) = VFFB1(2) = 0 to 1.2 V VFFB1(2) = 0 V; Increase COMP1,2 until GATE(H)1,2 starts switching Duty cycle = 50%, Note 3. VFFB1(2) = 0 V - - - 0.30 40 - 0.0 - 150 0.45 70 0.4 - - 300 0.60 100 1.5 1.1 300 ns V mV A V ns Test Conditions Min Typ Max Unit 3. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION PACKAGE PIN # 16 Lead SO Narrow 1 2 3 4 5 6 7 8 PIN SYMBOL GATE(H)1 GATE(L)1 PGND1 LGND SGND VFFB1 VFB1 COMP1 FUNCTION High Side Switch FET driver pin for the channel 1 FET. Low Side Synchronous FET driver pin for the channel 1 FET. High Current ground for the GATE(H)1 and GATE(L)1 pins. Logic ground. All control circuits are referenced to this pin. IC substrate connection. Ground sense for the internal reference. Input for the channel 1 PWM comparator. Error amplifier inverting input for channel 1. Channel 1 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation. The same capacitor provides Soft Start timing for channel 1. This pin also disables the channel 1 output when pulled below 0.3 V. Channel 2 Error Amp output. PWM Comparator reference input. A capacitor to LGND provides Error Amp compensation and Soft Start timing for channel 2. Channel 2 output is disabled when this pin is pulled below 0.3 V. 9 COMP2 http://onsemi.com 4 CS5421 PACKAGE PIN DESCRIPTION (continued) PACKAGE PIN # 16 Lead SO Narrow 10 11 12 13 14 15 16 VCC PIN SYMBOL VFB2 VFFB2 ROSC VCC PGND2 GATE(L)2 GATE(H)2 ROSC FUNCTION Error amplifier inverting input for channel 2. Input for the channel 2 PWM comparator. A resistor from this pin to ground sets switching frequency. Input Power supply pin. High Current ground for the GATE(H)2 and GATE(L)2 pins. Low Side Synchronous FET driver pin for the channel 2 FET. High Side Switch FET driver pin for the channel 2 FET. BIAS CURRENT SOURCE GEN RAMP1 RAMP2 CLK1 VFFB1 VFFB2 OSC CLK2 PWM Comparator 1 FAULT S Reset Dominant R VCC GATE(H)1 VCC GATE(L)1 - + 8.6 V 7.8 V - VCC - 0.25 V E/A OFF 1.0 V + SGND - + 5.0 A VFB - + - + - + + + S Q FAULT Set Dominant R PGND1 RAMP1 0.45 V VCC S FAULT Reset Dominant R VCC GATE(L)2 GATE(H)2 - + PWM Comparator 2 RAMP2 PGND2 0.45 V E/A1 E/A OFF 1.0 mA FAULT - - + 1.0 V E/A2 COMP1 VFB2 COMP2 LGND Figure 2. Block Diagram http://onsemi.com 5 CS5421 APPLICATIONS INFORMATION THEORY OF OPERATION The CS5421 is a dual power supply controller that utilizes the V2 control method. Two synchronous V2 buck regulators can be built using a single controller. The fixed-frequency architecture, driven from a common oscillator, ensures a 180 phase differential between channels. V2 Control Method The V2 method of control uses a ramp signal that is generated by the ESR of the output capacitors. This ramp is proportional to the AC current through the main inductor and is offset by the DC output voltage. This control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. The V2 method differs from traditional techniques such as voltage mode control, which generates an artificial ramp, and current mode control, which generates a ramp using the inductor current. PWM Comparator - GATE(H) + GATE(L) RAMP VFFB Slope Compensation COMP Error Signal Output Voltage Feedback VFB - + Error Amplifier Reference Voltage Figure 3. V2 Control with Slope Compensation time to the output load step is not related to the crossover frequency of the error signal loop. The error signal loop can have a low crossover frequency, since the transient response is handled by the ramp signal loop. The main purpose of this `slow' feedback loop is to provide DC accuracy. Noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. Enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. Line and load regulation is drastically improved because there are two independent control loops. A voltage mode controller relies on the change in the error signal to compensate for a deviation in either line or load voltage. This change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulations. A current mode controller maintains a fixed error signal during line transients, since the slope of the ramp signal changes in this case. However, regulation of load transients still requires a change in the error signal. The V2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. The stringent load transient requirements of modern microprocessors require the output capacitors to have very low ESR. The resulting shallow slope in the output ripple can lead to pulse width jitter and variation caused by both random and synchronous noise. A ramp waveform generated in the oscillator is added to the ramp signal from the output voltage to provide the proper voltage ramp at the beginning of each switching cycle. This slope compensation increases the noise immunity particularly at higher duty cycle (above 50%). Startup The V2 control method is illustrated in Figure 3. The output voltage generates both the error signal and the ramp signal. Since the ramp signal is simply the output voltage, it is affected by any change in the output, regardless of the origin of that change. The ramp signal also contains the DC portion of the output voltage, allowing the control circuit to drive the main switch to 0% or 100% duty cycle as required. A variation in line voltage changes the current ramp in the inductor, which causes the V2 control scheme to compensate the duty cycle. Since any variation in inductor current modifies the ramp signal, as in current mode control, the V2 control scheme offers the same advantages in line transient response. A variation in load current will affect the output voltage, modifying the ramp signal. A load step immediately changes the state of the comparator output, which controls the main switch. The comparator response time and the transition speed of the main switch determine the load transient response. Unlike traditional control methods, the reaction The CS5421 features a programmable Soft Start function, which is implemented through the Error Amplifier and the external Compensation Capacitor. This feature prevents stress to the power components and overshoot of the output voltage during start-up. As power is applied to the regulator, the CS5421 Undervoltage Lockout circuit (UVL) monitors the IC's supply voltage (VCC). The UVL circuit prevents the MOSFET gates from switching until VCC exceeds the 8.6 V threshold. A hysteresis function of 800 mV improves noise immunity. The Compensation Capacitor connected to the COMP pin is charged by a 30 A current source. When the capacitor voltage exceeds the 0.4 V offset of the PWM comparator, the PWM control loop will allow switching to occur. The upper gate driver GATE(H) is activated turning on the upper MOSFET. The current then ramps up through the main inductor and linearly powers the output capacitors and load. When the regulator output voltage exceeds the COMP pin voltage minus the 0.4 V PWM comparator offset http://onsemi.com 6 CS5421 threshold and the artificial ramp, the PWM comparator terminates the initial pulse. 8.6 V VIN current. For better transient response, several high frequency and bulk output capacitors are usually used. Out-of-Phase Synchronization VCOMP 0.45 V VFB GATE(H)1 GATE(H)2 UVLO STARTUP tS NORMAL OPERATION Figure 4. Idealized Waveforms Normal Operation In out-of-phase synchronization, the turn-on of the second channel is delayed by half the switching cycle. This delay is supervised by the oscillator, which supplies a clock signal to the second channel which is 180 out of phase with the clock signal of the first channel. The advantages of out-of-phase synchronization are many. Since the input current pulses are interleaved with one another, the overlap time is reduced. The effect of this overlap reduction is to reduce the input filter requirement, allowing the use of smaller components. In addition, since peak current occurs during a shorter time period, emitted EMI is also reduced, thereby reducing shielding requirements. Overvoltage Protection During normal operation, the duty cycle of the gate drivers remains approximately constant as the V2 control loop maintains the regulated output voltage under steady state conditions. Variations in supply line or output load conditions will result in changes in duty cycle to maintain regulation. Gate Charge Effect on Switching Times When using the onboard gate drivers, the gate charge has an important effect on the switching times of the FETs. A finite amount of time is required to charge the effective capacitor seen at the gate of the FET. Therefore, the rise and fall times rise linearly with increased capacitive loading, according to the following graphs. Average Fall Time 90 80 Fall/Rise Time (ns) 70 60 50 40 30 20 10 0 0 1 2 3 4 Load (nF) 5 6 7 8 Average Rise Time Overvoltage Protection (OVP) is provided as a result of the normal operation of the V2 control method and requires no additional external components. The control loop responds to an overvoltage condition within 200 ns, turning off the upper MOSFET and disconnecting the regulator from its input voltage. This results in a crowbar action to clamp the output voltage preventing damage to the load. The regulator remains in this state until the overvoltage condition ceases. Remote Sense When the load is far away from the regulator, the long feedback traces can cause additional voltage drop and induce noise which affects the accuracy of voltage regulation. A separate signal ground is provided to improve the noise immunity of remote voltage sensing. The 1.0 V reference voltage of the error amplifiers is directly referenced to this ground and no large currents flow through this ground during normal operation. The noise immunity and regulation accuracy can be improved significantly. Output Enable On/Off control of the regulator outputs can be implemented by pulling the COMP pins low. The COMP pins must be driven below the 0.4 V PWM comparator offset voltage in order to disable the switching of the GATE drivers. DESIGN GUIDELINES Definition of the design specifications Figure 5. Average Rise and Fall Times Transient Response The 200 ns reaction time of the control loop provides fast transient response to any variations in input voltage and output current. Pulse-by-pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. Since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitors during the time required to slew the inductor The output voltage tolerance can be affected by any or all of the following reasons: 1. buck regulator output voltage setpoint accuracy; 2. output voltage change due to discharging or charging of the bulk decoupling capacitors during a load current transient; http://onsemi.com 7 CS5421 3. output voltage change due to the ESR and ESL of the bulk and high frequency decoupling capacitors, circuit traces, and vias; 4. output voltage ripple and noise. Budgeting the tolerance is left up to the designer who must take into account all of the above effects and provide an output voltage that will meet the specified tolerance at the load. The designer must also ensure that the regulator component temperatures are kept within the manufacturer's specified ratings at full load and maximum ambient temperature. Selecting Feedback Divider Resistors 800 700 Frequency (kHz) 600 500 400 300 200 100 10 20 30 40 ROSC (kW) 50 60 VOUT R1 VFB R2 Figure 7. Switching Frequency Selecting the Switching Frequency Figure 6. Selecting Feedback Divider Resistors The feedback pins (VFB1(2)) are connected to externalresistor dividers to set the output voltages. The error amplifier is referenced to 1.0 V and the output voltage is determined by selecting resistor divider values. Resistor R1 is selected based on a design trade-off between efficiency and output voltage accuracy. The output voltage error can be estimated due to the bias current of the error amplifier neglecting resistor tolerance: Error% + 1 10*6 1.0 R1 100% Selecting the switching frequency is a trade-off between component size and power losses. Operation at higher switching frequencies allows the use of smaller inductor and capacitor values. Nevertheless, it is common to select lower frequency operation because a higher frequency results in lower efficiency due to MOSFET gate charge losses. Additionally, the use of smaller inductors at higher frequencies results in higher ripple current, higher output voltage ripple, and lower efficiency at light load currents. The value of the oscillator resistor is designed to be linearly related to the switching period. If the designer prefers not to use Figure 7 to select the necessary resistor, the following equation quite accurately predicts the proper resistance for room temperature conditions. ROSC + 21700 * fSW 2.31fSW R2 can be sized after R1 has been determined: R2 + R1 VOUT * 1.0 1.0 where: ROSC = oscillator resistor in k; fSW = switching frequency in kHz. Selection of the Output Inductor Calculating Duty Cycle The duty cycle of a buck converter (including parasitic losses) is given by the formula: Duty Cycle + D + VOUT ) (VHFET ) VL) VIN ) VLFET * VHFET * VL where: VOUT = buck regulator output voltage; VHFET = high side FET voltage drop due to RDS(ON); VL = output inductor voltage drop due to inductor wire DC resistance; VIN = buck regulator input voltage; VLFET = low side FET voltage drop due to RDS(ON). The inductor should be selected based on its inductance, current capability, and DC resistance. Increasing the inductor value will decrease output voltage ripple, but degrade transient response. There are many factors to consider in selecting the inductor including cost, efficiency, EMI and ease of manufacture. The inductor must be able to handle the peak current at the switching frequency without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. There are a variety of materials and types of magnetic cores that could be used for this application. Among them are ferrites, molypermalloy cores (MPP), amorphous and powdered iron cores. Powdered iron cores are very commonly used. Powdered iron cores are very suitable due http://onsemi.com 8 CS5421 to its high saturation flux density and have low loss at high frequencies, a distributed gap and exhibit very low EMI. The minimum value of inductance which prevents inductor saturation or exceeding the rated FET current can be calculated as follows: (VIN(MIN) * VOUT)VOUT LMIN + fSW VIN(MIN) ISW(MAX) DI IL(VALLEY) + IOUT * L 2.0 where: IL(VALLEY) = inductor valley current. Selection of the Output Capacitors where: LMIN = minimum inductance value; VIN(MIN) = minimum design input voltage; VOUT = output voltage; fSW = switching frequency; ISW(MAX) - maximum design switch current. The inductor ripple current can then be determined: V DIL + OUT L (1.0 * D) fSW where: IL = inductor ripple current; VOUT = output voltage; L = inductor value; D = duty cycle. fSW = switching frequency The designer can now verify if the number of output capacitors will provide an acceptable output voltage ripple (1.0% of output voltage is common). The formula below is used: DVOUT DIL + ESRMAX These components must be selected and placed carefully to yield optimal results. Capacitors should be chosen to provide acceptable ripple on the regulator output voltage. Key specifications for output capacitors are their ESR (Equivalent Series Resistance), and ESL (Equivalent Series Inductance). For best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. In order to determine the number of output capacitors the maximum voltage transient allowed during load transitions has to be specified. The output capacitors must hold the output voltage within these limits since the inductor current can not change with the required slew rate. The output capacitors must therefore have a very low ESL and ESR. The voltage change during the load current transient is: DVOUT + DIOUT ESL ) ESR ) tTR Dt COUT Rearranging we have: ESRMAX + DVOUT DIL where: ESRMAX = maximum allowable ESR; VOUT = 1.0% x VOUT = maximum allowable output voltage ripple ( budgeted by the designer ); IL = inductor ripple current; VOUT = output voltage. The number of output capacitors is determined by: Number of capacitors + ESRCAP ESRMAX where: IOUT / t = load current slew rate; IOUT = load transient; t = load transient duration time; ESL = Maximum allowable ESL including capacitors, circuit traces, and vias; ESR = Maximum allowable ESR including capacitors and circuit traces; tTR = output voltage transient response time. The designer has to independently assign values for the change in output voltage due to ESR, ESL, and output capacitor discharging or charging. Empirical data indicates that most of the output voltage change (droop or spike depending on the load current transition) results from the total output capacitor ESR. The maximum allowable ESR can then be determined according to the formula: ESRMAX + DVESR DIOUT where: ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheet). The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform): DI IL(PEAK) + IOUT ) L 2.0 where: VESR = change in output voltage due to ESR (assigned by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the formula: Number of capacitors + ESRCAP ESRMAX where: IL(PEAK) = inductor peak current; IOUT = load current; IL = inductor ripple current. where: ESRCAP = maximum ESR per capacitor (specified in manufacturer's data sheet). ESR = maximum allowable ESR. http://onsemi.com 9 CS5421 The actual output voltage deviation due to ESR can then be verified and compared to the value assigned by the designer: DVESR + DIOUT ESRMAX Similarly, the maximum allowable ESL is calculated from the following formula: ESLMAX + DVESL DI Dt Selection of the Input Inductor A common requirement is that the buck controller must not disturb the input voltage. One method of achieving this is by using an input inductor and a bypass capacitor. The input inductor isolates the supply from the noise generated in the switching portion of the buck regulator and also limits the inrush current into the input capacitors upon power up. The inductor's limiting effect on the input current slew rate becomes increasingly beneficial during load transients. The worst case is when the load changes from no load to full load (load step), a condition under which the highest voltage change across the input capacitors is also seen by the input inductor. The inductor successfully blocks the ripple current while placing the transient current requirements on the input bypass capacitor bank, which has to initially support the sudden load change. The minimum inductance value for the input inductor is therefore: DV LIN + (dI dt)MAX The input of the MOSFET acts as if it were a small capacitor, which the driving circuit must charge at turn on. The lower the drive impedance, the higher the rate of rise of VGS, and the faster the turn-on time. Power dissipation in the switching MOSFET consists of 1) conduction losses, 2) leakage losses, 3) turn-on switching losses, 4) turn-off switching losses, and 5) gate-transitions losses. The latter three losses are proportional to frequency. The most important aspect of FET performance is the Static Drain-To-Source On-Resistance (RDS(ON)), which effects regulator efficiency and FET thermal management requirements. The On-Resistance determines the amount of current a FET can handle without excessive power dissipation that may cause overheating and potentially catastrophic failure. As the drain current rises, especially above the continuous rating, the On-Resistance also increases. Its positive temperature coefficient is between +0.6%/C and +0.85%/C. The higher the On-Resistance the larger the conduction loss is. Additionally, the FET gate charge should be low in order to minimize switching losses and reduce power dissipation. Both logic level and standard FETs can be used. Voltage applied to the FET gates depends on the application circuit used. Both upper and lower gate driver outputs are specified to drive to within 1.5 V of ground when in the low state and to within 2.0 V of their respective bias supplies when in the high state. In practice, the FET gates will be driven rail-to-rail due to overshoot caused by the capacitive load they present to the controller IC. Selection of the Switching (Upper) FET where: LIN = input inductor value; V = voltage seen by the input inductor during a full load swing; (dI/dt)MAX = maximum allowable input current slew rate. The designer must select the LC filter pole frequency so that at least 40 dB attenuation is obtained at the regulator switching frequency. The LC filter is a double-pole network with a slope of -2, a roll-off rate of -40 dB/dec, and a corner frequency: fC + 1.0 2p LC The designer must ensure that the total power dissipation in the FET switch does not cause the power component's junction temperature to exceed 150C. The maximum RMS current through the switch can be determined by the following formula: IL(PEAK)2 ) (IL(PEAK) ) IL(VALLEY)2 D IRMS(H) + 3.0 IL(VALLEY)) where: L = input inductor; C = input capacitor(s). SELECTION OF THE POWER FET FET Basics where: IRMS(H) = maximum switching MOSFET RMS current; IL(PEAK) = inductor peak current; IL(VALLEY) = inductor valley current; D = duty cycle. Once the RMS current through the switch is known, the switching MOSFET conduction losses can be calculated: PRMS(H) + IRMS(H)2 RDS(ON) The use of the MOSFET as a power switch is propelled by two reasons: 1) Its very high input impedance; and 2) Its very fast switching times. The electrical characteristics of a MOSFET are considered to be those of a perfect switch. Control and drive circuitry power is therefore reduced. Because the input impedance is so high, it is voltage driven. where: PRMS(H) = switching MOSFET conduction losses; IRMS(H) = maximum switching MOSFET RMS current; RDS(ON) = FET drain-to-source on-resistance http://onsemi.com 10 CS5421 The upper MOSFET switching losses are caused during MOSFET switch-on and switch-off and can be determined by using the following formula: PSWH + PSWH(ON) ) PSWH(OFF) V + IN IOUT (tRISE ) tFALL) 6.0T where: PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses; VIN = input voltage; IOUT = load current; tRISE = MOSFET rise time (from FET manufacturer's switching characteristics performance curve); tFALL = MOSFET fall time (from FET manufacturer's switching characteristics performance curve); T = 1/fSW = period. The total power dissipation in the switching MOSFET can then be calculated as: PHFET(TOTAL) + PRMS(H) ) PSWH(ON) ) PSWH(OFF) where: PSWL = lower FET switching losses; VSD = lower FET source-to-drain voltage; ILOAD = load current; Non-overlap time = GATE(L)-to-GATE(H) or GATE(H)-to-GATE(L) delay (from CS5421 data sheet Electrical Characteristics section); fSW = switching frequency. The total power dissipation in the synchronous (lower) MOSFET can then be calculated as: PLFET(TOTAL) + PRMS(L) ) PSWL where: PLFET(TOTAL) = Synchronous (lower) FET total losses; PRMS(L) = Switch Conduction Losses; PSWL = Switching losses. Once the total power dissipation in the synchronous FET is known the maximum FET switch junction temperature can be calculated: TJ + TA ) [PLFET(TOTAL) RQJA] where: PHFET(TOTAL) = total switching (upper) MOSFET losses; PRMS(H) = upper MOSFET switch conduction Losses; PSWH(ON) = upper MOSFET switch-on losses; PSWH(OFF) = upper MOSFET switch-off losses; Once the total power dissipation in the switching FET is known, the maximum FET switch junction temperature can be calculated: TJ + TA ) [PHFET(TOTAL) RQJA] where: TJ = MOSFET junction temperature; TA = ambient temperature; PLFET(TOTAL) = total synchronous (lower) FET losses; RJA = lower FET junction-to-ambient thermal resistance. Control IC Power Dissipation where: TJ = FET junction temperature; TA = ambient temperature; PHFET(TOTAL) = total switching (upper) FET losses; RJA = upper FET junction-to-ambient thermal resistance. Selection of the Synchronous (Lower) FET The power dissipation of the IC varies with the MOSFETs used, VCC, and the CS5421 operating frequency. The average MOSFET gate charge current typically dominates the control IC power dissipation. The IC power dissipation is determined by the formula: PCONTROL(IC) + ICC1VCC1 ) PGATE(H)1 ) PGATE(L)1 ) PGATE(H)2 ) PGATE(L)2 The switch conduction losses for the lower FET can be calculated as follows: PRMS(L) + IRMS2 + [IOUT RDS(ON) (1.0 * D)]2 RDS(ON) where: PRMS(L) = lower MOSFET conduction losses; IOUT = load current; D = Duty Cycle; RDS(ON) = lower FET drain-to-source on-resistance. The synchronous MOSFET has no switching losses, except for losses in the internal body diode, because it turns on into near zero voltage conditions. The MOSFET body diode will conduct during the non-overlap time and the resulting power dissipation (neglecting reverse recovery losses) can be calculated as follows: PSWL + VSD ILOAD non-overlap time fSW where: PCONTROL(IC) = control IC power dissipation; ICC1 = IC quiescent supply current; VCC1 = IC supply voltage; PGATE(H) = upper MOSFET gate driver (IC) losses; PGATE(L) = lower MOSFET gate driver (IC) losses. The upper (switching) MOSFET gate driver (IC) losses are: PGATE(H) + QGATE(H) fSW VCC where: PGATE(H) = upper MOSFET gate driver (IC) losses; QGATE(H) = total upper MOSFET gate charge at VCC; fSW = switching frequency; The lower (synchronous) MOSFET gate driver (IC) losses are: PGATE(L) + QGATE(L) fSW VGATE(L) http://onsemi.com 11 CS5421 where: PGATE(L) = lower MOSFET gate driver (IC) losses; QGATE(L) = total lower MOSFET gate charge at VCC; fSW = switching frequency; The junction temperature of the control IC is primarily a function of the PCB layout, since most of the heat is removed through the traces connected to the pins of the IC. Adding External Slope Compensation THERMAL MANAGEMENT Thermal Considerations for Power MOSFET Today's voltage regulators are expected to meet very stringent load transient requirements. One of the key factors in achieving tight dynamic voltage regulation is low ESR. Low ESR at the regulator output results in low output voltage ripple. The consequence is, however, that very little voltage ramp exists at the control IC feedback pin (VFB), resulting in increased regulator sensitivity to noise and the potential for loop instability. In applications where the internal slope compensation is insufficient, the performance of the CS5421-based regulator can be improved through the addition of a fixed amount of external slope compensation at the output of the PWM Error Amplifier (the COMP pin) during the regulator off-time. Referring to Figure 7, the amount of voltage ramp at the COMP pin is dependent on the gate voltage of the lower (synchronous) FET and the value of resistor divider formed by R1and R2. VSLOPECOMP + VGATE(L) R2 R1 ) R2 -t (1.0 * e t ) As the plastic packaging of a semiconductor will deteriorate at high temperatures, it is necessary to limit the junction temperature of the control IC and power MOSFETs to maintain high reliability. Most semiconductor devices have a maximum junction temperature of 150C, and manufacturers recommend operating their products at lower temperatures if at all possible. Power dissipation in a semiconductor devices results in the generation of heat in the pin junctions at the surface of the chip. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the resistive properties of the package molding compound. The magnitude of the thermal gradient is expressed in manufacturer's data sheets as JA, or junction-to-air thermal resistance. The on-chip junction temperature can be calculated if JA, the air temperature at the surface of the IC, and the on-chip power dissipation are known. TJ + TA ) (PDQJA) where: VSLOPECOMP = amount of slope added; VGATE(L) = lower MOSFET gate voltage; R1, R2 = voltage divider resistors; t = tON or tOFF (switch off-time); = RC constant determined by C1 and the parallel combination of R1, R2 neglecting the low driver output impedance. The artificial voltage ramp created by the slope compensation scheme results in improved control loop stability provided that the RC filter time constant is smaller than the off-time cycle duration (time during which the lower MOSFET is conducting). It is important that the series combination of R1 and R2 is high enough in resistance to avoid loading the GATE(L) pin. COMP CCOMP CS5421 R2 C1 R1 where: TJ = IC or FET junction temperature (in degrees C); TA = ambient temperature (in degrees C); PD = power dissipated by part in question (in watts); JA = junction-to-ambient thermal resistance (in degrees C per watt). The value for JA can be found in the Absolute Maximum Ratings table on page 2 of this datasheet. Note that this value is different for every package style and every manufacturer. The junction temperature should be calculated for all semiconductor devices as a part of the design phase in order to ensure that the devices are operated below the manufacturer's maximum junction temperature specification. If any component's temperature exceeds the manufacturer's maximum temperature, some form of heatsink will be required. Heatsinking improves the thermal performance of any component. Adding a heatsink will reduce the magnitude of JA by providing a larger surface area for the transfer of heat from the component to the surrounding air. Typical heatsinking techniques include the use of commercial heatsinks for devices in TO-220 packages, or printed circuit board techniques such as thermal bias and large copper foil areas for surface mount packages. When choosing a heatsink, it is important to realize that JA is comprised of several components: QJA + QJC ) QCS ) QSA GATE(L) To Synchronous FET Figure 8. Small RC Filter Provides the Proper Voltage Ramp at the Beginning of Each On-Time Cycle where: JC = the junction-to-case thermal resistance (in degrees C per watt); CS = the case-to-sink thermal resistance (in degrees C per watt); http://onsemi.com 12 CS5421 SA = the sink-to-ambient thermal resistance (in degrees C per watt). The value for JC is included in the component manufacturer's data sheets. Its value is dependent on the mold compound and lead frames used in assembly of the semiconductor device in question. CS is the thermal impedance from the surface of the case to the heatsink. This component of the thermal resistance is dependent on the roughness of the heatsink and component as well as on the pressure applied between the two. CS can be reduced by using thermal pads or by applying a thin layer of thermal grease between the case and the heatsink. Such materials reduce the air gap normally found between the heatsink and the case and provide a better path for thermal energy. Values of CS are found in catalogs published by manufacturers of heatsinks and thermal compounds. Finally, SA is the thermal impedance from the heatsink to the ambient environment. SA is the important parameter when selecting a heatsink. Low values of SA allow increased power dissipation without exceeding the maximum junction temperature of the component. Values of SA are found in catalogs published by heatsink manufacturers. The basic equation for selecting a heatsink is: P+ TJ * TA QJC ) QCS ) QSA input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of the power component to minimize routing distance will also help to reduce emissions. LAYOUT GUIDELINES When laying out the CPU buck regulator on a printed circuit board, the following checklist should be used to ensure proper operation of the CS5421. 1. Rapid changes in voltage across parasitic capacitors and abrupt changes in current in parasitic inductors are major concerns for a good layout. 2. Keep high currents out of sensitive ground connections. 3. Avoid ground loops as they pick up noise. Use star or single point grounding. 4. For high power buck regulators on double-sided PCB's a single ground plane (usually the bottom) is recommended. 5. Even though double sided PCB's are usually sufficient for a good layout, four-layer PCB's are the optimum approach to reducing susceptibility to noise. Use the two internal layers as the power and GND planes, the top layer for power connections and component vias, and the bottom layers for the noise sensitive traces. 6. Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7. The MOSFET gate traces to the IC must be short, straight, and wide as possible. 8. Use fewer, but larger output capacitors, keep the capacitors clustered, and use multiple layer traces with heavy copper to keep the parasitic resistance low. 9. Place the switching MOSFET as close to the +5.0 V input capacitors as possible. 10. Place the output capacitors as close to the load as possible. 11. Place the COMP capacitor as close as possible to the COMP pin. 12. Connect the filter components of the following pins: VFB, VOUT, and COMP to the GND pin with a single trace, and connect this local GND trace to the output capacitor GND. 13. Place the VCC bypass capacitors as close as possible to the IC. where: PD = power dissipated by part in question (in watts); TJ = IC or FET junction temperature (in degrees C); TA = ambient temperature (in degrees C); JC = the junction-to-case thermal resistance (in degrees C per watt); CS = the case-to-sink thermal resistance (in degrees C per watt); SA = the sink-to-ambient thermal resistance (in degrees C per watt). The choice of heatsink is dependent on the value of SA required to keep the calculated junction temperature at the given level of power dissipation below the component manufacturer's maximum junction temperature. EMI MANAGEMENT As a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. When designing for compliance with EMI/EMC regulations, additional components may be added to reduce noise emissions. These components are not required for regulator operation and experimental results may allow them to be eliminated. The http://onsemi.com 13 CS5421 PACKAGE DIMENSIONS SO-16 D SUFFIX CASE 751B-05 ISSUE J -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S http://onsemi.com 14 CS5421 Notes http://onsemi.com 15 CS5421 V2 is a trademark of Switch Power, Inc. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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